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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
15
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Terminal Functions
Signal Group
Signal Name
Type
Description
Ungated inputs DCKEn, DODTn
1.35V/1.5V
CMOS Inputs1
DRAM corresponding register function pins not associated with
Chip Select.
Chip Select
gated inputs
DAn, DBAn, DRAS,
DCAS, DWE
1.35V/1.5V
CMOS Inputs1
DRAM corresponding register inputs, re-driven only when either
chip select is LOW. If both chip selects are low the register maintains
the state of the previous input clock cycle at its outputs
Chip Select
inputs
DCS0, DCS1
1.35V/1.5V
CMOS Inputs1
DRAM corresponding register Chip Select signals. These pins
initiate DRAM address/command decodes, and as such exactly one
will be low when a valid address/command is present which should
be re-driven.
DCS2, DCS3
1.35V/1.5V
CMOS Inputs1
DRAM corresponding register Chip Select signals when QuadCS
mode is enabled. DCS2 and DCS3 inputs are disabled when QuadCS
mode is disabled.
Re-driven
outputs
QxAn, QxBAn, QxCSn,
QxCKEn, QxODTn,
QxRAS, QxCAS,
QxWE
1.35V/1.5V
CMOS Outputs2
Outputs of the register, valid after the specified clock count and
immediately following a rising edge of the clock. x is A or B;
outputs are grouped as A or B and may be enabled or disabled via
RC0.
Parity input
PAR_IN
1.35V/1.5V
CMOS Inputs1
Input parity is received on pin PAR_IN and should maintain parity
across the Chip Select Gated inputs (see above), at the rising edge of
the input clock, one input clock cycle after corresponding data and
one or both chip selects are LOW.
Parity error
output
ERROUT
Open drain
When LOW, this output indicates that a parity error was identified
associated with the address and/or command inputs. ERROUT will
be active for two clock cycles, and delayed by 3 clock cycles to the
corresponding input data
Clock inputs
CK, CK
1.35V/1.5V
CMOS Inputs1
Differential master clock input pair to the PLL; has weak internal
pull-down resistors (10K
~100K.
Feedback
FBIN, FBIN
1.35V/1.5V
CMOS Inputs1
Feedback clock input
Clock
FBOUT, FBOUT
1.35V/1.5V
CMOS Outputs2
Feedback clock output
Clock Outputs
Yn, Yn
1.35V/1.5V
CMOS Outputs2
Re-driven Clock
Miscellaneous
inputs
RESET
CMOS3
Active low asynchronous reset input. When LOW, it causes a reset of
the internal latches and disables the outputs, thereby forcing the
outputs to float. Once RESET becomes high the Q outputs get
enabled and are driven LOW (ERROUT is driven high) until the first
access has been performed. RESET also resets the ERROUT signal.
MIRROR
CMOS3
Selects between two different ballouts for front or back operation.
When the MIRROR input is high, the device Input Bus Termination
(IBT) is turned off on all inputs, except the DCSn and DODTn
inputs.
QSCEN
CMOS3
Enables the QuadCS mode. The QSCEN input has a weak internal
pullup resistor (10K
- 100K).
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